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Cadence Design Systems
Digital Design Engineer Intern — Security IP & DMA Subsystem
- Built an automated Python/Tcl flow to extract and consolidate synthesis and power metrics from Cadence Genus and Joules into the production pipeline.
- Developed performance measurements for per-algorithm throughput and latency across the cryptographic IP family (PQC, AES, ChaCha20-Poly1305, ARIA, TRNG, PUF) to support feature closure against specifications.
- Validated concurrent DMA execution across multiple cryptographic engines, achieving up to 3× throughput (20–70% fewer cycles), with no added hardware and equivalent area and energy.
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Auto Hall
Forecasting & Optimization Intern
- Developed a time-series forecasting prototype in Python using automatic ARIMA model selection (Auto-ARIMA) to predict vehicle sales and anticipate ordering requirements.
- Analyzed historical sales and ordering patterns to support inventory planning, balancing stock availability, delivery lead times and transportation costs across multiple brands.
- Built an order-optimization algorithm that reduced monthly delivery costs by up to a factor of 4; presented cost–availability trade-offs to management, which adopted the results.
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CNRS — ISM / IM2NP
Optoelectronics Intern
- Fabricated ZnO-based pellets for a research project exploring a polarization-based sky-navigation system inspired by natural celestial polarization.
- Characterized the photoresponse of samples by measuring electrical current under optical illumination, using Keysight equipment and optical fiber.
- Supported experimental prototyping and sample fabrication using laboratory tools including 3D printing, and processed measurement data in Python.
featured projects
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AES Verification Environment
SystemVerilog testbench, C++ DPI layer and Python golden model connected over sockets to verify an AES-128 core against a reference model. Randomized verification, socket-based co-simulation and coverage reporting.
AES
Coverage
Cryptography
DPI-C
Python
RTL Verification
SystemVerilog
TensorDMA
SystemVerilog multi-channel DMA with round-robin arbitration, AXI4 read master and backpressure-aware FIFO. Verified, synthesized and measured for PPA (Performance, Power, Area).
AXI4
DMA
FIFO
PPA
RTL Design
Synthesis
SystemVerilog