my projects.

AES Verification Environment

AES Verification Environment

SystemVerilog testbench, C++ DPI layer and Python golden model connected over sockets to verify an AES-128 core against a reference model. Randomized verification, socket-based co-simulation and coverage reporting.

AES
Coverage
Cryptography
DPI-C
Python
RTL Verification
SystemVerilog
Source
TensorDMA

TensorDMA

SystemVerilog multi-channel DMA with round-robin arbitration, AXI4 read master and backpressure-aware FIFO. Verified, synthesized and measured for PPA (Performance, Power, Area).

AXI4
DMA
FIFO
PPA
RTL Design
Synthesis
SystemVerilog
Source
HeartPix — ECG Acquisition System

HeartPix — ECG Acquisition System

Complete acquisition chain: fabricated electrodes, analog front-end, signal conditioning, digital filtering and real-time display on an STM32 with OLED matrix.

ECG
Embedded Systems
PCB Design
STM32
Signal Processing
Source
ASCON128 Hardware Accelerator

ASCON128 Hardware Accelerator

Implemented the lightweight ASCON-128 authenticated encryption (AEAD) algorithm in SystemVerilog and deployed it on FPGA.

AEAD
Cryptography
Digital Design
FPGA
SystemVerilog
Source
Advanced Analog Design

Advanced Analog Design

NMOS transistor characterization and common-source amplifier design in Cadence Virtuoso. Gain and bias point optimization with schematic simulation.

Amplifier
Analog Design
Cadence Virtuoso
NMOS
SPICE
Source
DVWA Penetration Testing

DVWA Penetration Testing

Comprehensive penetration testing report on DVWA (Damn Vulnerable Web Application), covering XSS, SQL Injection, CSRF and other common web vulnerabilities.

CSRF
Pentesting
SQL Injection
Web Security
XSS
Source